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|---|---|---|
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Generate a N bits two inputs AND with an output power of drive named modelname.
Valid drive are : 2 or 4.
| GENLIB_MACRO(DPGEN_AND2, "model_and2_32"
                       , F_BEHAV|F_PLACE
                       , 32
                       , 2
                       );
GENLIB_LOINS( "model_and2_32"
            , "instance1_and2_32"
            , "i1[31:0]"
            , "i0[31:0]"
            ,  "q[31:0]"
            , "vdd", "vss", NULL
            );
     | 
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| DPGEN_NAND4 | Up | DPGEN_AND3 |